When reading the content of a memory cell in a memory cell arrangement, with increasing speed of the read operation, so-called glitches may occur within the read path, e.g., glitches may occur on a data bus of the memory cell arrangement in case of a non valid data read operation. In a conventional memory cell arrangement, a valid bit may only gate the read data after the data read from a memory cell has been latched in a data latch using combinatorial circuit elements, in other words, logic gates implementing a correspondingly provided logic function. However, the combinatorial circuit elements may cause glitches due to signal races of the signals being transferred via the combinatorial circuit elements.